In modern DRAM devices, small dimensions and high capacitance value per unit area of the capacitor are desirable characteristics for achieving a high charge storage capacity. A DRAM capacitor is normally formed by at least two layers of polysilicon films and one layer of a dielectric insulator. The DRAM devices have been named as dynamic because the cells can retain information only for a limited period of time and that they must be read and refreshed periodically. This is in contrast to a static random access memory (SRAM) cell which does not require periodic refresh signals in order to retain stored data.
A typical DRAM cell includes a field effect transistor and a storage capacitor. When DRAM cells were first developed, planar type storage capacitors which occupy large wafer surface areas were used. However, in modern memory devices where the dimensions of the device are continuously being miniaturized, methods for reducing the chip real estate required for a capacitor becomes more important. One of the methods encompasses a design of stacking a capacitor over the bit line on the surface of a silicon substrate in order to increase the specific capacitance of a storage capacitor. The stacked capacitor is formed by a layer of a dielectric material such as silicon dioxide or oxide-nitride-oxide sandwiched between two layers of polysilicon. The effective capacitance of the stacked capacitor cell is increased over that of a conventional planar cell due to its increased surface area.
Other techniques have also been tried in achieving higher capacitance on limited chip real estate. For instance, one method stores charges vertically in a trench which requires a deep trench formation resulting in significant processing difficulties. The stacked capacitor approach is therefore a well accepted and popular approach for achieving higher specific capacitance in a DRAM storage capacitor.
One of the possible configurations for a stacked capacitor is a fin-type stacked capacitor in which multiple number of fins generally formed of polysilicon is used as the bottom electrode for the capacitor. The increased surface areas on the fins contribute to the increased specific capacitance. A typical method for forming a fin-type stacked capacitor is shown in FIGS. 1A through 1G.
Referring initially to FIG. 1A, wherein a conventional semiconductor structure is shown. The semiconductor 10 consists of a silicon substrate 12 onto which a field oxide region 14 is first formed to isolate the field effect transistors 16. The field oxide 14 is typically formed by a LOCOS method during which silicon is thermally oxidized to form and to expand vertically into a silicon oxide region. The field effect transistor 16 is generally formed by first growing a thin oxide layer (not shown) on the silicon substrate as a gate oxide layer, and then forming a polysilicon gate electrode 18 on top of the gate oxide layer. The polysilicon layer which forms the gate electrode 18 is also used to form word line 22 over the field oxide 14 to provide interconnections between the transistors and the peripheral circuits on the chip. After lightly doped drain areas are formed in the substrate by an ion implantation method and sidewall spacers 24 are formed on the gate electrode 18, the transistor formation is completed by forming source/drain contact areas 26, 28 in the silicon substrate 12 adjacent to the gate electrode 18. A thick insulating layer 32 can be deposited over the gate electrode 18 and the word line 22 for electrical insulation. A silicon nitride etch stop layer 34 is then deposited over a planarized top surface of the insulating layer 32. The planarization process for the insulating layer 32 can be carried out advantageously by a chemical mechanical polishing technique.
In a conventional fin-type stacked capacitor process, as shown in FIG. 1B, oxide layers 36, 38 and polysilicon layer 40 are deposited by a chemical vapor deposition technique on top of a silicon nitride etch step layer 34. The number of layers of polysilicon deposited is optional depending on the number offins ofthe stacked capacitor desired. On top of the final oxide layer 38, a photoresist layer 42 is then deposited and patterned. This is shown in FIG. 1C. Conventional photolithographic techniques and anisotropic plasma dry etching method are then used to form a contact opening 46. This is shown in FIG. 1D. The oxide layers 32, 36 and 38 and the polysilicon layer 40 are etched away to form the window opening such that a node contact 48 on the active area of the source/drain 26 is formed. The multiple layers of oxide and polysilicon can be etched in a reactive ion etching method by an etchant gas mixture containing fluorine or other etchant gas.
After the opening of the contact window 46 and the formation of the node contact 48 for the stacked capacitor to be built, a polysilicon layer 52 is blanket deposited over the oxide layer 38 and into the contact opening 46. The polysilicon layer 52 can be deposited by a low pressure to chemical vapor deposition (LPCVD) technique. The polysilicon layer 52 is then patterned by a photoresist layer (not shown) to define a bottom electrode 56. The anisotropic etching process for defining the bottom electrode 56 stops at the oxide layer 36. In the next processing step, a wet chemical etching method is used to remove the oxide layers 36 and 38 while maintaining the bottom electrode 56 intact and thus forming a freestanding fin-type polysilicon electrode 56 for the capacitor. This is shown in FIG. 1G. Onto the bottom electrode 56, a thin dielectric layer (not shown) and a thick polysilicon layer (not shown) are then deposited and patterned to form the capacitor dielectric and the capacitor top plate.
The conventional process for forming a fin-type stacked capacitor is a complicated process which requires multiple deposition steps for forming the multiple layers of oxide and polysilicon on top of the active device such that the fins can be formed. The process requires multiple deposition steps conducted in a series of processing chambers. It is a time consuming process which leads to low yield for the fabrication of fin-type stacked capacitors.
It is therefore an object of the present invention to provide a method for forming a fin-type DRAM stacked capacitor that does not have the drawbacks and shortcomings of a conventional capacitor forming process.
It is another object of the present invention to provide a method for forming a fin-type DRAM stacked capacitor by depositing multiple layers of different insulating materials in a single deposition process.
It is a further object of the present invention to provide a method for forming a fin-type DRAM stacked capacitor by depositing multiple layers of different insulating materials that have different etch rates in a single process chamber.
It is another further object of the present invention to provide a method for forming a fin-type DRAM stacked capacitor by first forming multiple layers of doped oxide and non-doped oxide insulating materials which have different etch rates.
It is still another object of the present invention to provide a method for forming a fin-type DRAM stacked capacitor by first depositing multiple layers of different oxide materials that have an etch rate ratio of greater than 3 when etched in a wet etch process.
It is yet another object of the present invention to provide a method for forming a fin-type DRAM stacked capacitor by first depositing multiple layers of different oxide materials, dry etching a contact opening through the layers, and then wet etching the oxide layers which have different etch rates so that a zig-zag configuration in the contact opening is formed.
It is still another further object of the invention to provide a method for forming a fin-type DRAM stacked capacitor by first forming a zig-zag configured contact opening and then depositing a polysilicon bottom electrode into the opening.
It is yet another further object of the present invention to provide a method for forming a fin-type DRAM stacked capacitor by first depositing multiple layers of doped and undoped oxide layers and then wet etching such layers by an etchant containing NH.sub.4 OH and H.sub.2 O.sub.2 at an etch rate ratio of at least 3.